1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device having a notched gate, and more particularly, to a method for fabricating a semiconductor device having a notched gate wherein the semiconductor device is capable of forming a shallow junction through a low-energy ion implantation process, while maintaining reliability in an oxide gate.
2. Description of the Related Art
When a semiconductor device is fabricated on a silicon substrate, an electric field of high strength is generated in an interface, or junction, region between a doping region and a channel region doped with high-density impurity on the bottom of a gate electrode of the substrate. Such an electric field of high strength continuously causes hot carriers to flow in the direction of the gate electrode, particularly at the bottom of the gate oxide layer, exposing the thin and weak gate oxide layer of about 40 to 100 Å in thickness to possible damage.
To address this issue, a lightly doped drain LDD region is fabricated between the highly doped drain region and the channel region on the substrate. Such an LDD region provides a transition region between the highly doped drain and the channel region to lower the strength of the electric field generated in the adjacent channel region and the gate oxide layer, and therefore decreases the flow of hot carriers generated by the electric field.
Referring to FIG. 1, in the conventional approach an LDD region 104 is formed including a gate electrode 110 and an isolation region of a field oxide 102 on the silicon substrate 100. Field oxide regions 102 are separately located on both sides of the gate electrode 110. A source or a drain region 106 is respectively formed between the gate electrode 110 and the field oxide 102.
In doping an impurity on the silicon substrate 100 to fabricate a source/drain region 106, the substrate 100 generally forms an LDD region 104 with a lightly doped impurity. The lightly doped substrate, for example including approximately 5×1013 B atom/cm2, forms a P-well in the negatively doped substrate, and the lightly doped substrate, for example with about 5×1013 As atom/cm2, forms an N-well in the positively doped substrate.
After depositing an oxide layer on the gate electrode 110, the oxide layer is etched anisotropically to form an oxide spacer 113 at the side walls of the gate electrode 110. A deep source/drain implanting process fabricates the highly doped source/drain region (N+ well or P+ well, 106) in the substrate 100 exposed between the oxide spacer (a gate spacer, 113) and the isolation layer of the field oxide 102.
Such an LDD region can eliminate the problem of hot carriers, but this approach can also result in deterioration of the gate oxide layer 111. Additionally, the resistance of the LDD region is higher than a comparable highly doped region because lighter dopant levels in the LDD region reduces electrical conductivity in the silicon substrate.
Such high resistance in the current passage between the source and drain regions deteriorates performance of the semiconductor device, even in the case of lower source voltages in the range of 2 to 3 V. Application of ever-lower voltages to integrated circuits adopted in portable computers such as a laptop computer remains an important design consideration. Therefore, it is not generally acceptable that the performance of the semiconductor device, including the LDD region, is deteriorated with the application of lower voltages.
It is therefore preferable that high-strength electric fields and hot carriers between the channel region and the highly doped drain region on the substrate be avoided, without increasing the resistance of the conventional LDD region.
In addition, as transistors of ever-smaller scale are developed, for example less than 0.1 μm, mitigation of a phenomenon referred to as the short channel effect (SCE) becomes an increasingly important consideration. To improve performance of the semiconductor device and to solve the above described problem, others have fabricated a shallow junction by utilizing a low energy implantation process. The conventional dry etching process forms a gate polysilicon layer 112 after the gate polysilicon layer 112 is deposited, and grows a gate poly oxide layer 114 to cure plasma damage to the gate polysilicon layer 112 during the dry etching process.
However, when a source/drain ion implanting process is applied through the gate poly oxide layer 114, the resistance in the source/drain region becomes higher because most of the dopants reside in the gate poly oxide layer 114. This can especially occur when the source/drain ion implanting process is a low energy ion implanting process. It is therefore desirable to ensure reliability of the gate electrode 110, without increasing resistance in the source/drain region.